1. Field of the Invention
The present invention generally relates to semiconductor processes, and more particularly to a method for fabricating a bit line contact between two adjacent gate conductor stacks by utilizing a sacrificial polysilicon layer and spin-on glass (SOG) during the fabrication of a Trench-DRAM device.
2. Description of the Prior Art
A memory chip is an integrated circuit (IC) made of millions of transistors and capacitors. In the most common form of computer memory, dynamic random access memory (DRAM), a MOS transistor and a storage capacitor are paired to create a memory cell, which represents a single bit of data. Memory cells are etched onto a silicon wafer in an array of columns (bit liners) and rows (word lines). The intersection of a bitline and wordline constitutes the address of the memory cell. The storage capacitor holds the bit of information. The MOS transistor acts as a switch that lets the control circuitry on the memory chip read the storage capacitor or change its state. The storage capacitor typically comprises a top electrode, a storage node, and a capacitor dielectric layer. As DRAMs are manufactured with increasing densities, the memory cells necessarily are made smaller and smaller and packed closer and closer together to pack as much memory into as small a space as possible. The increased density drives the word lines (or bit lines) closer tog-ether increasing the coupling between adjacent lines and also challenges the conventional lithographic methods for transferring tiny feature images such as a bit line contact pattern.
FIG. 1 to FIG. 5 are schematic cross-sectional diagrams illustrating a conventional method for fabricating a bit line contact between two adjacent gate conductor stacks 12 and 14. As shown in FIG. 1, on a main surface 11 of a semiconductor substrate 10, at least two gate conductor stacks 12 and 14 are provided. Each of the gate conductor stacks 12 and 14 generally comprises a gate dielectric layer 22, a conductive layer 24 and a silicon nitride cap layer 26. A bit line contact area 42 and a non-bit line contact area 44 are defined over the gate conductor stacks 12 and 14. The bit line contact area 42 is approximately above the area between the gate conductor stacks; 12 and 14. Typically, after the formation of the gate conductor stacks 12 and 14, a silicon nitride liner 32 is deposited on the semiconductor substrate 10. A borophosphosilicate glass (BPSG) layer 36 is then deposited on the silicon nitride liner 32.
As shown in FIG. 2, a chemical mechanical polishing (CMP) process is then carried out to polish the BPSG layer 36 to the silicon nitride liner 32. As shown in FIG. 3, a TEOS-oxide layer 38 is deposited on the remaining BPSC layer 36 and on the exposed silicon nitride liner 32. A photoresist pattern 52 is then formed on the TEOS-oxide layer 38 by using conventional lithographic methods. The photoresist pattern 52 has an opening 54 exposing the bit line contact area 42 between the gate conductor stacks 12 and 14.
As shown in FIG. 4, using the photoresist pattern 52 as an etching hard mask, an anisotropic etching process is performed to etch the TEOS-oxide layer 38, the BPSG 36 and the silicon nitride liner 32 through the opening 54, thereby forming a bit line contact hole 62. Simultaneously, a silicon nitride spacer 64 is formed on sidewall of the gate conductor stacks 12 and 14. The photoresist pattern 52 is then removed.
Finally, as shown in FIG. 5, the bit line contact hole 62 is filled with conductive materials such as metals or the like to form a bit line contact plug 64. Generally, the resultant bit line contact plug 64 is about 8000-angstrom height from the main surface 11 of the semiconductor substrate 10. The TEOS-oxide layer 38 has a thickness of about 3000 angstroms.
However, the above-described prior art method has several drawbacks. First, since the shrinkage of the bit line contact area 42, precise and accurate pattern transfer using conventional lithographic methods becomes a major challenge. As the bit line contact area 42 shrinks to below 90 nm, it often needs so-called Imaging Enhancement Technology (IET) to successfully transfer such small bit line contact pattern from a photo mask to a photoresist layer on a wafer. The process window is therefore narrowed. Further, it is difficult to clean up a bit line contact hole having a depth of about 8000 angstroms and a critical dimension of about 90 nm by using dry or wet etching methods. Some undesired residuals might clog the bit line contact hole. Another shortcoming is that the above-described prior art method uses silicon nitride liner 32. A part of the silicon nitride liner 32 is etched into a silicon nitride spacer 64 on sidewall of the gate conductor stacks 12 and 14. In operation, the silicon nitride spacer 64 leads to higher parasitic capacitance, which adversely affects the performance of the memory device.
Accordingly, it is the primary object of the present invention to provide a method for fabricating a bit line contact between two adjacent gate conductor stacks by utilizing a sacrificial polysilicon layer and spin-on glass (SOG) during the fabrication of a Trench-DRAM device, thereby solving the above-described problems.
According to the claimed in invention, a method for fabricating a bit line contact hole is provided. A substrate having a main surface is prepared. At least two adjacent gate conductor stacks are provided on the main surface. A bit line contact area and a non-bit line contact area are defined over the main surface. The bit line contact area is directly above an area between the two adjacent gate conductor stacks. Each of the gate conductor stacks has a top surface and sidewalls. A silicon oxide liner is deposited on the top surface and sidewalls of each of the gate conductor stacks. A sacrificial layer is thereafter deposited on the silicon oxide liner. A first chemical mechanical polishing (CMP) is carried out to polish the sacrificial layer. A spin-on-glass (SOG) layer is then coated onto the remaining sacrificial layer and onto the exposed top surface of the gate conductor stacks. A photoresist pattern is formed on the SOG layer masking the bit line contact area. Using the photoresist pattern as a hard mask, the SOG layer, the sacrificial layer, and the silicon oxide liner not covered by the photoresist pattern is etched away. The photoresist pattern is then removed, leaving the SOG layer, the sacrificial layer, and the silicon oxide liner within the bit line contact area intact. A silicon nitride liner is deposited on the SOG layer within the bit line contact area, the partial top surface and sidewalls of the gate conductor stacks. A dielectric layer is then deposited over the silicon nitride liner. A second CMP is performed to polish the dielectric layer to stop on the SOG layer. The remaining SOG layer and the sacrificial layer within the bit line contact area are selectively removed to form the bit line contact hole.
Other objects, advantages, and novel features of the claimed invention will become more clearly and readily apparent from the following detailed description when taken in conjunction with the accompanying drawings.